Modern consumer electronics, such as cellular phones, digital cameras, and music players, are packing more integrated circuits into an ever shrinking physical space with expectations for decreasing cost. Numerous technologies have been developed to meet these requirements. Some of the research and development strategies focus on new package technologies while others focus on improving the existing and mature package technologies. Research and development in the existing package technologies may take a myriad of different directions. This packaging excerpt limits the discussion to existing package technology improvements from improved manufacturing processes, package structures, performance, and stacking structures.
Pad-up quad flat non-leaded (QFN) is a mature package technology but represents less than 2% of the semiconductor gross market share out of the QFN total manufacturing volume of 18.6% in 2003. The low market penetration stems from QFN architectures that have hanging leads on the outer leads portion resulting in the package sides having interconnectivity rather than at the conventional surface mount plane (the package bottom). Most surface mount technology (SMT) end-users found it impractical to mount packages vertically or be required to use external sockets to a printed circuit board (PCB).
Another cause for the low market penetration for the pad-up QFN package is that most QFN manufacturing for the SMT interface used a saw singulation method. The cost of diamond saw blades continues to increase resulting in an overall cost increase of the QFN package technology.
An alternative to the saw singulation method, punch singulation provides a cost effective option. The punch tool exerts a dynamic cutting force on the package particularly for large QFN package sizes having thicker package profiles. The punch singulation method maturity extends the various improvement options for the QFN package technology.
Wire bonding processes become critical and difficult to control due thermosonic energy transmission into the hanging leads, which result in leads that bounce during the wire bonding. Package moldability performance is heavily reliant on the lead frame coverlay taping processes quality to hold the leads in place prior to molding. It is not viable to have differential height lead structures unsupported during the wire bonding process as taping hinders the use of a protruded islands heater block design. These complications resulted in reduced development for differential height lead structures design, except a few applications in the memory module packaging industry.
While punch singulation solved some of the problems, it also created some other critical problems. The leads being raised on the external portion of the interconnecting pad increases the risk for lead deflection during punch singulation resulting in defects such as distorted leads, metal burr, wire bond stitch cracking and metal bridging. Lead deflection also results in degraded package integrity prompting mold compound and metal lead delamination. Delamination causes moisture penetration, package cracks, and moisture resistance test (MRT) failure.
Thus, a need still remains for a non-leaded integrated circuit package that leverages improved manufacturing techniques while providing packaging features to meet the new market demands. In view of the ever-increasing need to save costs and improve efficiencies, it is more and more critical that answers be found to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.